1. Field of the Invention
The present application relates to semiconductor integrated circuit design, specifically to Phase Locked Loop (PLL) design in the semiconductor integrated circuit.
2. Description of the Related Art
Generally, PLL circuits are used to provide specific clock frequencies for a circuit. PLL circuits are designed to output specific frequency with a limited amount of jitter, however due to the variations in the designs and manufacturing for example, process, voltage and temperature (PVT), the output of the PLL may exceed the jitter limits and thus the “effective” clock frequency of the PLL may vary from the designed output. When PLL circuit locks at different effective frequency than what it is designed for, functional failures may occur on the chip. When the effective locked frequency of the PLL is unknown, it becomes difficult to debug the integrated circuit. During the production phase, it becomes difficult to determine whether any functional failures are due to the malfunction of other circuits on the chip or the actual PLL output itself.
Further, during manufacturing, integrated circuits are graded according to the operational speed based on the effective clock frequency. The speed of operation of an integrated circuit depends upon the frequency locked by the PLL in the integrated circuit. Thus, it is critical to determine the effective frequency locked by the PLL. Various peripheral measurement devices are used to estimate the effective PLL lock frequency. These external testing methods consume considerable amount of time to thoroughly test each integrated circuit and result in significant production delays. Therefore, an on-chip system and method are needed to determine the effective locked frequency of PLLs.